In systems for carrying out serial transmission of image data as main data, in order to transmit voice data as ancillary data, a format is required which has high compatibility with conventional formats without increasing the number of transmission cables.
The international publication of international patent application, WO 00/16525, discloses a method of transmitting ancillary data in correspondence with the pulse width of a clock signal, which is used for transmitting main data, by pulse-width-modulating the clock signal. This method allows the ancillary data to be transmitted without increasing the number of transmission cables.
FIG. 1 shows a configuration of a conventional data transmission system using such a method. As shown in FIG. 1, this data transmission system includes a transmitting circuit 10 which inputs main and ancillary data and a clock signal to transmit serial data and a transmission clock signal, a receiving circuit 20 which receives the transmitted serial data and transmission clock signal to output the main and ancillary data and clock signal, data transmission cables 30 which are used for transmitting the serial data, and a clock signal transmission cable 31 which is used for transmitting the transmission clock signal.
The transmitting circuit 10 is constructed of a main data transmitting circuit 11 and a binary pulse-width-modulating circuit 12. For example, the transmitting circuit 10 is supplied with RGB three lines of 8-bit image data, i.e., 24-bit (=3×8-bit) image data as the input main data, the input clock signal, and one-bit voice data as the input ancillary data. In the main data transmitting circuit 11, the input main data are converted into the serial data by using the input clock signal, and are transmitted as three channels of serial data. Furthermore, in the binary pulse-width-modulating circuit 12, the input clock signal is binary pulse-width-modulated by using the input ancillary data, and then transmitted as the transmission clock signal.
The receiving circuit 20 is constructed of a main data receiving circuit 21 and a binary pulse-width-demodulating circuit 22. In the binary pulse-width-demodulating circuit 22, the transmission clock signal is demodulated to obtain output ancillary data and an output clock signal. In the main data receiving circuit 21, the three channels of serial data are converted into parallel data by using the output clock signal so as to obtain output main data.
FIG. 2 shows the operation of the binary pulse-width-modulating circuit as shown in FIG. 1. The transmission clock signal is generated by setting the pulse width of the input clock signal to be at (50+a) % when the input ancillary data is “1”, and by setting the pulse width of the input clock signal to be at (50−a) % when the input ancillary data is “0”.
However, as shown in FIG. 2, when values of the input ancillary data are biased toward “1” or “0”, the average pulse width of the clock signal will deviate from 50%, resulting in biasing DC balance of the clock signal. This causes a problem of increasing jitter of the clock signal and deteriorating transmission quality of the whole system. Particularly when optical transmission is used, DC component cannot be transmitted, and therefore, the biased DC balance has a great influence.